The present invention generally relates to one-time-programmable (xe2x80x9cOTPxe2x80x9d) bit cells and in particular, to an OTP bit cell with a latch circuit having selectively programmable floating gate transistors.
OTP bit cells are commonly used for permanent or durable programming of bits in a system. OTP memory cells are a particularly popular type of OTP bit cell. OTP memory cells, however, are generally current sensing devices employing references and sense amplifiers. Therefore, they are prone to erroneous readings due to degradation of cell current over time. To avoid failure, or at least prolong the period of time before such failure, multiple OTP memory cells are sometimes placed in parallel to store a single bit of information. Although this arrangement may protect against charge loss from a single OTP memory cell causing a functional failure, the added OTP memory cells increase circuit size and consequently, device cost.
The use of latch circuits in OTP bit cells is advantageous, because they amplify current differences in generating differential voltage outputs rather than sensing current magnitudes. Consequently, latch circuits are not as readily prone to errors due to degradation of cell current, do not require the same reference and sense amplifier circuitry that OTP memory cells do, nor do they require the redundancy employed in OTP memory cells to reduce the effects of cell current degradation. Therefore, the use of latch circuits as OTP bit cells promise enhanced reliability and cost savings as compared to OTP memory cells.
Accordingly, an object of the present invention is to provide an OTP bit cell with a latch circuit that provides reliable and predictable results throughout its operational life.
Another object is to provide such an OTP bit cell that is cost effective to manufacture.
Still another object is to provide a method for programming such an OTP bit cell that is easy to perform in the field, as well as in the factory.
These and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is an OTP bit cell including floating gate transistors, and transistors coupled to the floating gate transistors so as to act as a latch circuit. After one of the floating gate transistors is selectively programmed by increasing a voltage across its source and drain so as to reduce its threshold voltage, a current differential is generated through the floating gate transistors and consequently, a differential voltage output of the latch circuit results having a logic state that corresponds to that selection and is the same each time when read.
Another aspect is a method for programming an OTP bit cell including first and second floating gate transistors, first and second PMOS transistors, and first and second NMOS transistors coupled together and to high and low reference voltages so as to form a latch circuit, and third and fourth NMOS transistors coupled to the first and the second floating gate transistors, the method comprising: applying write input voltages to the third and fourth NMOS transistors while raising the high reference voltage so as to program one, but not the other of the first and the second floating gate transistors.